Datasheet · 2020

Jadard JD9365DA-H3 — a-Si TFT LCD Single-Chip Driver Datasheet

Author: Jadard
Year: 2020
Type: Datasheet

jadard
jd9365da-h3
lcd driver
tft
mipi dsi

JD9365DA-H3 Data Sheet 800RGB x 1280 dot, 16.7M color, without internal GRAM, a-Si TFT LCD Single Chip Driver Version 0.01 2020/8/19 Confidential Copyright © JADARD V0.01 JD9365DA-H3 Index list: 1. Revision History ....................................................................................................................... 12 2. General Description ................................................................................................................. 13 3. Features ................................................................................................................................... 14 3.1. Display ..................................................................................................................................... 14 3.2. Display interface ...................................................................................................................... 14 3.3. Input voltage ranges ................................................................................................................ 14 3.4. Output voltage ranges ............................................................................................................. 14 3.5. Miscellaneous of chip .............................................................................................................. 15 4. Device Overview ...................................................................................................................... 16 4.1. Device Block Diagram .............................................................................................................. 16 4.2. LCD power generation scheme (DC/DC Converter) ................................................................ 17 4.3. Output voltage range .............................................................................................................. 18 4.4. DC/DC converter circuit........................................................................................................... 19 4.4.1. External power mode 1 (External AVDD/AVEE/VGH/VGL power) .......................................... 19 4.4.2. External power mode 2 (External AVDD/AVEE power) ........................................................... 20 4.4.3. DC/DC power mode 4 (AVDD/AVEE with FP7721 controlled by driver ic) .............................. 21 4.5. External Components Connection........................................................................................... 22 4.5.1. External power mode 1 (External AVDD/AVEE/VGH and VGL power) .................................... 22 4.5.2. External power mode 1 (External AVDD and AVEE power) .................................................... 23 4.5.3. DC/DC power mode 4 (AVDD/AVEE with FP7721 controlled by driver ic) .............................. 24 5. Maximum layout resistance .................................................................................................... 25 6. Pin description ......................................................................................................................... 26 7. Interface .................................................................................................................................. 31 7.1. DSI system interface ................................................................................................................ 31 7.1.1. Command mode, Video mode and Virtual Channel................................................................ 34 7.1.2. Power-up Sequence Example .................................................................................................. 36 7.1.3. DSI Format ............................................................................................................................... 37 P-2 August 19, 2020 V0.01 JD9365DA-H3 7.1.4. DSI Protocol ............................................................................................................................. 39 7.1.5. Multiple Packets per Transmission ......................................................................................... 39 7.1.6. Endian Policy ........................................................................................................................... 41 7.1.7. Packet Structure ...................................................................................................................... 42 7.1.8. Long Packet ............................................................................................................................. 43 7.1.9. Short Packet ............................................................................................................................ 45 7.1.10. Common Packet Elements....................................................................................................... 46 7.1.11. Data Identifier Byte ................................................................................................................. 46 7.1.12. Virtual Channel Identifier – VC field, DI[7:6] ........................................................................... 46 7.1.13. Data Type Field DT[5:0] ........................................................................................................... 46 7.1.14. ECC ........................................................................................................................................... 47 7.1.15. DSI packet ................................................................................................................................ 48 7.1.16. Processor-sourced Packets ...................................................................................................... 48 7.1.17. Packed Pixel Stream, 16-bit Format, Long Packet ................................................................... 49 7.1.18. Packed Pixel Stream, 18-bit Format, Long Packet ................................................................... 50 7.1.19. Pixel Stream, 18-bit Loosely Format, Long Packet .................................................................. 51 7.1.20. Packed Pixel Stream, 24-bit Format, Long Packet ................................................................... 52 7.1.21. Peripheral to Processor Transmission ..................................................................................... 53 7.1.22. Appropriate Responses to Commands and ACK Requests ...................................................... 54 7.1.23. Peripheral-to-Processor Packet Description ........................................................................... 55 7.1.24. Format of Acknowledge and Error Report and Read Response Data Type............................. 56 7.1.25. Video Mode Interface Timing .................................................................................................. 58 7.1.26. Transmission Packet Sequences .............................................................................................. 58 7.1.27. Non-Burst sync pulse mode..................................................................................................... 60 7.1.28. Non-Burst sync event mode .................................................................................................... 61 7.1.29. Burst mode .............................................................................................................................. 62 7.1.30. Error-Correcting Code and Checksum ..................................................................................... 63 7.1.31. Error-Correcting Code(ECC) ..................................................................................................... 63 7.1.32. Checksum Generation for Long Packet Payloads .................................................................... 65 P-3 August 19, 2020 V0.01 JD9365DA-H3 7.1.33. DPHY ........................................................................................................................................ 66 7.1.34. Lane Module ............................................................................................................................ 66 7.1.35. Lane Module Type of Clock Lane, Data0, Data1 and Data2 .................................................... 66 7.1.36. Master and Slave ..................................................................................................................... 67 7.1.37. Lane States and Line Levels ..................................................................................................... 67 7.1.38. Bi-directional Data Lane Turnaround ...................................................................................... 68 7.1.39. Escape Mode ........................................................................................................................... 69 7.1.40. Remote Trigger ........................................................................................................................ 70 7.1.41. Low-Power Data Transmission(LPDT)...................................................................................... 70 7.1.42. Ultra-Low Power State(ULPS) .................................................................................................. 70 7.1.43. TE Trigger ................................................................................................................................. 71 7.1.44. High Speed Transmission......................................................................................................... 73 7.1.45. Burst Payload Data .................................................................................................................. 73 7.1.46. Start-of-Transmission .............................................................................................................. 73 7.1.47. End-of-Transmission ................................................................................................................ 74 7.1.48. High Speed Data Transmission ................................................................................................ 75 7.1.49. High Speed Clock Transmission ............................................................................................... 75 7.1.50. System Power state ................................................................................................................. 76 7.1.51. Initialization ............................................................................................................................. 76 7.1.52. Global Operation Flow Diagram .............................................................................................. 76 8. Gamma Structure Description ................................................................................................. 78 8.1. Adjustable gamma characteristic ............................................................................................ 78 8.2. Grayscale-Level adjustment control ........................................................................................ 79 8.2.1. Variable resister ratio & Voltage levels ................................................................................... 81 9. Function Description ............................................................................................................. 100 9.1. Tearing effect Line ................................................................................................................. 100 9.1.1. Tearing effect Line mode ....................................................................................................... 100 9.1.2. Tearing effect line timing ...................................................................................................... 102 9.2. Oscillator................................................................................................................................ 103 P-4 August 19, 2020 V0.01 JD9365DA-H3 9.3. Output pins Characteristics ................................................................................................... 104 9.4. Self-diagnostic Functions....................................................................................................... 105 9.4.1. Register loading detection .................................................................................................... 105 9.4.2. Functionality Detection ......................................................................................................... 106 9.5. Power on/off sequence ......................................................................................................... 107 9.5.1. General .................................................................................................................................. 107 9.5.2. Power on sequence for differential power mode ................................................................. 108 9.5.3. Power off sequence for differential power mode ................................................................. 111 9.5.4. Deep standby Flow ................................................................................................................ 117 9.6. Uncontrolled power off ......................................................................................................... 118 9.7. Content adaptive brightness control (CABC) function .......................................................... 119 9.7.1. Definition of the CABC ........................................................................................................... 119 9.7.2. Transition Time of the CABC.................................................................................................. 120 9.7.3. Minimum brightness setting of CABC function ..................................................................... 123 10. Command .............................................................................................................................. 124 10.1. Command List ........................................................................................................................ 124 10.1.1. Standard command ............................................................................................................... 124 10.1.2. Standard Command Accessibility .......................................................................................... 127 10.1.3. Standard Command Default Modes and Values ................................................................... 128 10.2. Command Description ........................................................................................................... 129 10.2.1. NOP (00h) .............................................................................................................................. 129 10.2.2. SWRESET: Software Reset (01h) ............................................................................................ 130 10.2.3. RDDIDIF: Read Display Identification Information (04h) ....................................................... 131 10.2.4. RDNUMPE: Read number of the parity errors (05h) ............................................................. 132 10.2.5. REDRD: Read Red Color (06h) ............................................................................................... 133 10.2.6. REDGREEN: Read Green Color (07h) ..................................................................................... 134 10.2.7. REDBLUE: Read Blue Color (08h) ........................................................................................... 135 10.2.8. RDDST: Read Display Status (09h) ......................................................................................... 136 10.2.9. RDDPM: Read Display Power Mode (0Ah) ............................................................................ 138 P-5 August 19, 2020 V0.01 JD9365DA-H3 10.2.10. RDDMATCDL: Read Display MADCTL (0Bh) ........................................................................... 139 10.2.11. RDDCOLMOD: Read Display COLMOD (0Ch) ......................................................................... 140 10.2.12. Read Display Image Mode (0Dh) ........................................................................................... 141 10.2.13. RDDSM: Read Display Signal Mode (0Eh).............................................................................. 142 10.2.14. RDDSDR: Read Display Self-Diagnostic Result (0Fh).............................................................. 143 10.2.15. SLPIN: Enter Sleep In Mode (10h) ......................................................................................... 144 10.2.16. SLPOUT: Exit Sleep In Mode (11h) ......................................................................................... 145 10.2.17. NORON: Enter Normal Mode (13h) ....................................................................................... 146 10.2.18. INVOFF: Display Inversion Off (20h) ...................................................................................... 147 10.2.19. INVON: Display Inversion On (21h) ....................................................................................... 148 10.2.20. ALLPOFF: All Pixel Off (22h) ................................................................................................... 149 10.2.21. ALLPON: All Pixel On (23h) .................................................................................................... 150 10.2.22. GAMSET: Gamma Set (26h) ................................................................................................... 151 10.2.23. DISPOFF: Display Off (28h) .................................................................................................... 152 10.2.24. DISPON: Display On (29h) ...................................................................................................... 153 10.2.25. TEOFF: Tearing Effect Line OFF (34h) .................................................................................... 154 10.2.26. TEON: Tearing Effect Line ON (35h) ...................................................................................... 155 10.2.27. MADCTL: Memory Access Control(36h) ................................................................................ 156 10.2.28. IDMOFF: Idle Mode Off (38h) ................................................................................................ 158 10.2.29. IDMON: Idle Mode On (39h) ................................................................................................. 159 10.2.30. COLMOD: Interface Pixel Format (3Ah)................................................................................. 160 10.2.31. Write Memory Continue (3Ch) .............................................................................................. 161 10.2.32. RAMRDCON: Read Memory Continue (3Eh) ......................................................................... 162 10.2.33. TESL: Set Tear Effect Scanline (44h) ...................................................................................... 163 10.2.34. GETSCAN: Get the Current Scanline (45h) ............................................................................ 164 10.2.35. WRDISBV: Write Display Brightness (51h) ............................................................................ 165 10.2.36. RDDISBV: Read Display Brightness Value (52h)..................................................................... 166 10.2.37. WRCTRLD: Write CTRL Display (53h) ..................................................................................... 167 10.2.38. RDCTRLD: Read CTRL Value Display (54h) ............................................................................. 168 P-6 August 19, 2020 V0.01 JD9365DA-H3 10.2.39. WRCABC: Write Content Adaptive Brightness Control (55h) ................................................ 169 10.2.40. RDCABC: Read Content Adaptive Brightness Control (56h) .................................................. 172 10.2.41. WRCABCMB: Write CABC Minimum Brightness (5Eh) .......................................................... 175 10.2.42. RDCABCMB: Read CABC Minimum Brightness (5Fh) ............................................................ 176 10.2.43. RDDDB: Read DDB Start (A1h) ............................................................................................... 177 10.2.44. RDDDBCON: Read DDB Continue (A8h) ................................................................................ 179 10.2.45. RDFCS: Read First Checksum (AAh) ....................................................................................... 180 10.2.46. RDCCS: Read Continue Checksum (AFh) ............................................................................... 181 10.2.47. RDID1: Read ID1 (DAh) .......................................................................................................... 182 10.2.48. RDID2: Read ID2 (DBh) .......................................................................................................... 183 10.2.49. RDID3: Read ID3 (DCh) .......................................................................................................... 184 11. Electrical Specifications ......................................................................................................... 185 11.1. Absolute maximum ratings ................................................................................................... 185 11.2. DC characteristics .................................................................................................................. 186 11.3. AC characteristics .................................................................................................................. 187 11.3.1. Reset input timings ................................................................................................................ 187 11.3.2. DSI D-PHY electronic characteristics ..................................................................................... 188 11.3.3. Timings for DSI Video mode .................................................................................................. 199 12. Chip information.................................................................................................................... 203 12.1. PAD assignment ..................................................................................................................... 203 13. Ordering Information ............................................................................................................ 204 P-7 August 19, 2020 V0.01 JD9365DA-H3 Figure list: Figure 4.1: LCD power generation scheme .......................................................................... 17 Figure 4.2: External power source(AVDD/AVEE/VGH/VGL) ................................................. 19 Figure 4.3: External power source(AVDD/AVEE) .................................................................. 21 Figure 4.4: DC/DC power(AVDD/AVEE) with FP7721 ........................................................... 21 Figure 7.1: DSI transmitter and receiver interface ............................................................... 31 Figure 7.2: DSI Layer ............................................................................................................. 32 Figure 7.3: Peripheral Power-Up Sequencing Example........................................................ 36 Figure 7.4: Basic HS Transmission Structure ........................................................................ 37 Figure 7.5: Two Lane HS Transmission Example .................................................................. 38 Figure 7.6: Three Lane HS Transmission Example ................................................................ 38 Figure 7.7: HS Transmission Examples with EoTp disabled .................................................. 40 Figure 7.8: HS Transmission Examples with EoTp enabled .................................................. 40 Figure 7.9: Endian Example (Long Packet) ........................................................................... 41 Figure 7.10: Long Packet Structure ...................................................................................... 43 Figure 7.11: Short Packet Structure ..................................................................................... 45 Figure 7.12: Data Identifier Byte .......................................................................................... 46 Figure 7.13: 16-bit per Pixel – RGB Color Format, Long Packet ........................................... 49 Figure 7.14: 18-bit per Pixel (Packed) – RGB Color Format, Long Packet ............................ 50 Figure 7.15: 18-bit per Pixel (Loosely Packed) – RGB Color Format, Long Packet ............... 51 Figure 7.16: 24-bit per Pixel – RGB Color Format, Long Packet ........................................... 52 Figure 7.17: Video Mode Interface Timing Legend .............................................................. 59 Figure 7.18: Video Mode Interface Timing: Non-Burst Transmission with Sync Start and End ............................................................................................................................... 60 Figure 7.19: Video Mode Interface Timing: Non-burst Transmission with Sync Events ...... 61 Figure 7.20: Video Mode Interface Timing: Burst Transmission .......................................... 62 Figure 7.21: 24-bit ECC generation Example ........................................................................ 63 Figure 7.22: Checksum Transmission ................................................................................... 65 Figure 7.23: 16-bit CRC Generation Using a Shift Register .................................................. 65 Figure 7.24: Lane Module Type ............................................................................................ 66 Figure 7.25: Line Levels ........................................................................................................ 67 Figure 7.26: Turnaround Procedure ..................................................................................... 68 Figure 7.27: Trigger-Reset Command in Escape Mode ........................................................ 69 Figure 7.28: Two Data Byte Low-Power Data Transmission Example .................................. 70 Figure 7.29: High-Speed Data Transmission in Bursts .......................................................... 75 Figure 7.30: Switching the Clock Lane between Clock Transmission and Low-Power Mode ...................................................................................................................................... 75 Figure 7.31: Data Lane Module State Diagram .................................................................... 76 Figure 7.32: Clock Lane Module State Diagram ................................................................... 77 Figure 8.1: Grayscale control ............................................................................................... 79 P-8 August 19, 2020 V0.01 JD9365DA-H3 Figure 8.2: Gamma resister stream and gamma reference voltage .................................... 80 Figure 9.1: Tearing Effect Line mode 1 .............................................................................. 100 Figure 9.2: TE Line Delay under mode 1 ............................................................................ 100 Figure 9.3: Tearing Effect Line mode 2 .............................................................................. 101 Figure 9.4: TE Line Output for TELINE setting .................................................................... 101 Figure 9.5: Tearing Effect Line Output signal ..................................................................... 101 Figure 9.6: Tearing Effect Line timing ................................................................................. 102 Figure 9.7: Tearing Effect Line definition of tf, tr ............................................................... 102 Figure 9.8: Register loading detection flow chart .............................................................. 105 Figure 9.9: Functionality detection flow chart................................................................... 106 Figure 9.10: Power off sequence for differential power mode.......................................... 109 Figure 9.11: Power off sequence for differential power mode.......................................... 115 Figure 9.12: Transition Time on Content Adaptive Brightness Control ............................. 120 Figure 9.13: Transition Time on Manual Setting ................................................................ 121 Figure 9.14: Transition Time on Combined Display Brightness ......................................... 122 Figure 11.1: Reset input timings ........................................................................................ 187 Figure 11.2: Electronic functions of a D-PHY transceiver .................................................. 188 Figure 11.3: HS and LP signal levels ................................................................................... 188 Figure 11.4: Input Glitch Rejections of Low-Power Receivers ........................................... 191 Figure 11.5: DDR Clock Definition ...................................................................................... 194 Figure 11.6: Data to Clock Timing Definitions .................................................................... 195 Figure 11.7: High-Speed Data Transmission in Bursts ........................................................ 197 Figure 11.8: Switching the Clock Lane between Clock Transmission and Low-Power Mode .................................................................................................................................... 198 Figure 11.9: Vertical Timings for DPI I/F............................................................................. 199 Figure 11.10: Horizontal Timing for DSI Video mode I/F ................................................... 201 P-9 August 19, 2020 V0.01 JD9365DA-H3 Table list: Table 4.1: Voltage configuration .......................................................................................... 18 Table 5.1: Maximum Layout Resistance ............................................................................... 25 Table 7.1: Data Types for supported Processor-sourced Packets ........................................ 48 Table 7.2: Data Types for Peripheral-sourced Packets ......................................................... 55 Table 7.3: Error Report Bit Definitions ................................................................................. 57 Table 7.4: Lane State Descriptions ....................................................................................... 68 Table 7.5: Escape Entry Codes.............................................................................................. 69 Table 7.6: Start-of-Transmission Sequence .......................................................................... 73 Table 7.7: End-of-Transmission Sequence ........................................................................... 74 Table 8.1: Gamma-Adjustment registers ............................................................................. 79 Table 8.2: VOP15~18 ............................................................................................................ 82 Table 8.3: VOP13/VOP14 ..................................................................................................... 83 Table 8.4: VOP11/VOP12...................................................................................................... 84 Table 8.5: VOP10 .................................................................................................................. 85 Table 8.6: VOP9 .................................................................................................................... 86 Table 8.7: VOP8 .................................................................................................................... 87 Table 8.8: VOP6/ VOP7......................................................................................................... 88 Table 8.9: VOP4/ VOP5......................................................................................................... 89 Table 8.10: VOP0~3 .............................................................................................................. 90 Table 8.11: VON15~18 ......................................................................................................... 91 Table 8.12: VON13/VON14 .................................................................................................. 92 Table 8.13: VON11/VON12 .................................................................................................. 93 Table 8.14: VON10 ............................................................................................................... 94 Table 8.15: VON9 ................................................................................................................. 95 Table 8.16: VON8 ................................................................................................................. 96 Table 8.17: VON6/ VON7...................................................................................................... 97 Table 8.18: VON4/ VON5...................................................................................................... 98 Table 8.19: VON0~3 ............................................................................................................. 99 Table 9.1: AC characteristics of Tearing Effect Line ........................................................... 102 Table 9.2: Output and I/O pins Characteristics .................................................................. 104 Table 9.3: Display Output Brightness Calculations ............................................................ 121 Table 9.4: Minimum Brightness Setting of the CABC Function - Example ......................... 123 Table 10.1: Standard command list .................................................................................... 126 Table 10.2: Standard Command Accessibility .................................................................... 127 Table 10.3: Standard Command Default Modes and Value ............................................... 128 Table 11.1: Absolute maximum ratings.............................................................................. 185 Table 11.2: DC characteristic .............................................................................................. 186 Table 11.3: Reset timings ................................................................................................... 187 Table 11.4: LP-TX DC Specifications ................................................................................... 190 P-10 August 19, 2020 V0.01 JD9365DA-H3 Table 11.5: LP-TX AC Specifications ................................................................................... 190 Table 11.6: LP-RX DC Specifications ................................................................................... 191 Table 11.7: LP-RX AC Specifications ................................................................................... 191 Table 11.8: Contention Detector DC Specifications ........................................................... 192 Table 11.9: HS Receiver DC Specifications ......................................................................... 193 Table 11.10: HS Receiver AC Specifications ....................................................................... 193 Table 11.11: Reverse HS Data Transmission Timing Parameters....................................... 195 Table 11.12: Data to Clock Timing Specifications .............................................................. 196 Table 11.13: Vertical Timings for RGB I/F ........................................................................... 200 Table 11.14: Horizontal Timings for DSI Video mode I/F ................................................... 202 P-11 August 19, 2020 V0.01 JD9365DA-H3 1. Revision History Version 0.00 0.01 Date 2020/08/17 2020/08/19 Description of modification New setup Update VDDD voltage typo. in P.17~18. P-12 August 19, 2020 V0.01 JD9365DA-H3 2. General Description The JD9365DA-H3 supports WXGA resolution driving controller. The JD9365DA-H3 is designed to provide a single-chip solution that combines a source driver, gate driver control, power supply circuit to drive a-Si TFT dot matrix LCD with 800RGBx1280 dots at maximum. The JD9365DA-H3 can be operated in low-voltage condition for the interface and integrated internal boosters that produce the liquid crystal voltage and the voltage follower circuit for liquid crystal driver. In addition, The JD9365DA-H3 also supports various driving functions to reduce the power consumption of a LCD system via software control. The JD9365DA-H3 is suitable for any small portable battery-driven and long-term driving products, such as Tablet, digital cellular phones and bi-directional pagers. P-13 August 19, 2020 V0.01 JD9365DA-H3 3. Features 3.1. Display  Single chip solution for a WXGA a-Si type LCD display  Resolution:  800RGB x LN*2  768RGB x LN*2  750RGB x LN*2  720RGB x LN*2  640RGB x LN*2  600RGB x LN*2  Display color modes  Full color mode:  16.7M colours (24-bit 8(R):8(G):8(B))  Reduce color mode:  262k colours (18-bit 6(R):6(G):6(B))  65k colours (16-bit 5(R):6(G):5(B))  8 colors (Idle mode on): 8 colors (3-bit binary mode) 3.2. Display interface  Display interface types supported  MIPI-DSI (Display Serial Interface) interface  Support DSI Version 1.1  Support D-PHY version 1.00 3.3. Input voltage ranges  I/O and interface power supply (IOVCC): 1.65V to 3.3V  High speed interface power supply (VCCH): 1.65V to 3.3V  Digital power supply (VCCD): 1.65V to 3.3V  When BOOSTM=”00”, ”01” (AVDD, AVEE is external power mode)  Analog power supply (VCI): 2.5V to 6.0V  DC/DC set-up supply (VCIP): 2.5V to 6.0V  When BOOSTM=”10” (AVDD, AVEE is internal DC/DC converter mode)  Analog power supply (VCI): 2.5V to 4.8V  DC/DC set-up supply (VCIP): 2.5V to 4.8V  OTP programming voltage (VPP): 7.5V ± 0.2V  Analog volatge range for AVDD to VSSP: 4.5V ~ 6.3V  Analog volatge range for AVEE to VSSP: -4.5V ~ -6.3V  Analog volatge frange for VCL to VSSP: -2.5V ~ -3.9V  Analog volatge range for VGH to VSSP: 7V ~ 20V  Analog volatge range for VGL to VSSP: -7V ~ -15V 3.4. Output voltage ranges  On module DC/DC converter P-14 August 19, 2020 V0.01 JD9365DA-H3  AVDD= +4.5V to +6.3V  AVEE= -4.5V to -6.3V  Positive source output voltage level: VGMP= +3.0V to 5.8V  Negative source output voltage level: VGMN= -3.0V to -5.8V  Positive gate driver output voltage level: VGH= 7 to 20V  Negative gate driver output voltage level: VGL=-7V to -15V  VCOM=-4.0V to 0V, a step=10mv 3.5. Miscellaneous of chip  Internal level shifter for Gate Driver control  Supports column / 1-dot / 2-dot / 4-dot / Z inversion  Gamma correction (1 preset gamma curve)  Internal Oscillator generation  CMOS compatible inputs  Proprietary multi phase driving for lower power consumption  GAS function for preventing image sticking when abnormal power off  Temperature range: -40 to +85 °C  On-chip OTP program voltage generator 